A continuing trend in semiconductor technology is to build integrated circuits with more and/or faster semiconductor devices. The drive toward this ultra large scale integration has resulted in continued shrinking of device and circuit dimensions and features. In integrated circuits having field-effect transistors, for example, one very important process step is the formation of the gate, source and drain regions for each of the transistors, and in particular the dimensions of the gate, source and drain regions. In many applications, the performance characteristics (e.g., switching speed) and size of the transistor are functions of the size (e.g., width) of the transistor's gate, and the placement of the source and drain regions there about. Thus, for example, a narrower gate tends to produce a higher performance transistor (e.g., faster) that is inherently smaller in size (e.g., narrower width).
As is often the case, however, as the devices shrink in size from one generation to the next, some of the existing fabrication techniques are not precise enough to be used in fabricating the next generation of integrated circuit devices. For example, spacers are used in conventional semiconductor devices to provide alignment of the source and drain regions to the gates in transistors. Minor differences in the shape of the spacers can alter the operational characteristics of the device. This is especially true for integrated circuits that have a plurality of similar devices that are meant to share common operating characteristics. Accordingly, there is a continuing need for more efficient and effective fabrication processes for forming semiconductor gates, spacers and regions that are more precisely controlled.